The present invention relates to an improved method and apparatus for implementing error correction coding (ECC) in a dynamic random access memory (DRAM) utilizing vertical ECC storage.
When storing and reading error correction codes (ECC) that are vertically placed in a dynamic random access memory (DRAM), a basic performance problem arises when the ECC check bits are calculated over bytes that are contained in two DRAM rows. Read-Modify-Write (RMW) and Read-Close Row-Open Row-Read operations must be performed across DRAM row boundaries which degrade performance and increase design complexity.
For example, consider a DRAM based memory that is vertically storing ECC and designed to generate one byte of ECC for every four bytes of data. With a page size or one row of this memory is 512 bytes and one DRAM module in this memory which has a byte wide data bus, this means the hardware must make five accesses to the memory module to obtain the four bytes of data (one word) and the one ECC byte. Examining the very first page of this memory it is immediately apparent there are 102 five byte words in this page or 510 bytes with two bytes left over. The left over bytes resent a problem, two bytes of the 103rd word are in the first DRAM page and the next two bytes of data along with the ECC byte are in the next page of memory.
An ordinary read of these bytes at the row boundaries requires a read of two bytes from the first page, closing that page (row), and then opening and accessing the next page (row). This is very time consuming. Writes that are less than four bytes to this area are even worse. Such writes require a read of two bytes form the first page, closing that page, opening the second page to read the next two bytes of data and the ECC byte, closing the second page, merging in the new data to be written and calculating the new ECC byte. Then the first page is opened again to write two bytes. Then the first page is closed and finally the second page is opened again to write the remaining two byte along with the ECC byte. This is very time consuming and very complex.
A principal object of the present invention is to provide improved methods and apparatus for implementing error correction coding (ECC) in a dynamic random access memory (DRAM) utilizing vertical ECC storage. Other objects are to provide such methods and apparatus substantially without negative effects and that overcome many of the disadvantages of prior art arrangements.
In brief, methods and apparatus for implementing error correction coding (ECC) in a dynamic random access memory (DRAM) utilizing vertical ECC storage. An integral number of available data blocks is identified for each page of the DRAM. Each data block includes a defined number of data and ECC bytes. Data and ECC bytes are stored in the identified integral number of data blocks for each page. The remaining bytes in each page are used as padding.
In accordance with features of the invention, address translation is provided utilizing the equation:
Y=X+X/4+{2xc3x97INT((X+X/4)/510)},
where X equals the logical address presented and Y equals the physical address and 510 represents 102 available data blocks for each page of the DRAM with each data block includes 5 bytes. A page number (P) can be calculated utilizing the following equation:
P=A/28+A/216+A/224+A/232+A/240+A/248+A/256+A/264+A/272+A/280+A/288+. . . ,
where A equals A=X+X/4.